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Q.

The ___ bus controller device decodes the signals to produce the control bus signal

A

internal

B

data

C

external

D

address

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1.

In 8086 microprocessor one of the following statements is not true?

A

coprocessor is interfaced in max mode.

B

coprocessor is interfaced in min mode.

C

I /O can be interfaced in max / min mode.

D

supports pipelining

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During a read operation the CPU fetches ________

A

a program instruction

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another address

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data itself

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The _______ is used to connect more microprocessor

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peripheral device

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cascade

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Register

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The 8086 fetches instruction one after another from __________ of memory

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queue

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stack

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segment

D

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