Question Discussion & Solution

MCQ

The most efficient way of handling parameter passing is by using ______

General purpose registers

Stacks

Memory locations

None of the mentioned

Community Discussion

No discussions yet. Be the first to start!

You must be logged in to participate in the discussion.

Similar Questions

MCQ

In case of nested subroutines the return addresses are stored in __________

System heap

Special memory buffers

Processor stack

Registers

Discussion

MCQ

The most Flexible way of logging the return addresses of the subroutines is by using _______

Registers

Stacks

Memory locations

None of the mentioned

Discussion

MCQ

The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i) The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user

i, ii and iv

ii and iii

iii and iv

Discussion

MCQ

The order in which the return addresses are generated and used is _________

LIFO

FIFO

Random

Highest priority

Discussion

MCQ

The location to return to, from the subroutine is stored in _______

TLB

MAR

Link registers

Discussion

Banking

Engineering

General

Medical

Question Discussion & Solution

Report Error

Community Discussion

Similar Questions

Report Error

Report Error

Report Error

Report Error

Report Error

More Computer Organization and Architecture Topics

Instruction set architecture

Cache Memory and Pipelining

Machine instructions and Addressing modes

Secondary Memory,Input Output interfce(DMA,Interrupts)

ALU data path and Control Unit

Cache Memory and its design

CPU design

Interrupts

Subroutines and Nesting

Direct Memory Access

PCI BUS

Mixed

Banking

Engineering

General

Medical

Question Discussion & Solution

report Report Error

forum Community Discussion

auto_awesome Similar Questions

report Report Error

report Report Error

report Report Error

report Report Error

report Report Error

category More Computer Organization and Architecture Topics

Instruction set architecture

Cache Memory and Pipelining

Machine instructions and Addressing modes

Secondary Memory,Input Output interfce(DMA,Interrupts)

ALU data path and Control Unit

Cache Memory and its design

CPU design

Interrupts

Subroutines and Nesting

Direct Memory Access

PCI BUS

Mixed

Report Error

Community Discussion

Similar Questions

Report Error

Report Error

Report Error

Report Error

Report Error

More Computer Organization and Architecture Topics