Menu

Question Discussion & Solution

MCQ

Q.

The fetch and execution cycles are interleaved with the help of ________

A

Modification in processor architecture

B

Clock

C

Special unit

D

Control unit

Community Discussion

No discussions yet. Be the first to start!

You must be logged in to participate in the discussion.

Login to Discuss

Similar Questions

MCQ

1.

The contention for the usage of a hardware device is called ______

A

Structural hazard

B

Stalk

C

Deadlock

D

None of the mentioned

Discussion

MCQ

2.

______ have been developed specifically for pipelined systems.

A

Utility software

B

peed up utilities

C

Optimizing compilers

D

None of the mentioned

Discussion

MCQ

3.

What is the high speed memory between the main memory and the CPU called?

A

Register Memory

B

Cache Memory

C

Storage Memory

D

Virtual Memory

Discussion

MCQ

4.

Each stage in pipelining should be completed within ___________ cycle.

A

1

B

2

C

3

D

4

Discussion

MCQ

5.

The number of sign bits in a 32-bit IEEE format is ____

A

1

B

11

C

9

D

23

Discussion

More Computer Organization and Architecture Topics

Instruction set architecture

17 MCQs

Cache Memory and Pipelining

20 MCQs

Machine instructions and Addressing modes

41 MCQs

Secondary Memory,Input Output interfce(DMA,Interrupts)

20 MCQs

ALU data path and Control Unit

15 MCQs

Cache Memory and its design

10 MCQs

CPU design

11 MCQs

Interrupts

24 MCQs

Subroutines and Nesting

10 MCQs

Direct Memory Access

15 MCQs

PCI BUS

20 MCQs

Mixed

10 MCQs