Question Discussion & Solution

MCQ

The registers, ALU and the interconnection between them are collectively called as _____ .

Process route

Information trail

Information path

Data path

Community Discussion

No discussions yet. Be the first to start!

You must be logged in to participate in the discussion.

Similar Questions

MCQ

Which of the following is/are true of the auto-increment addressing mode?I. It is useful in creating self-relocating code
II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation
III. The amount of increment depends on the size of the data item accessed

I only

II only

III only

II and III only

Discussion

MCQ

_______ is used to store data in registers .

D flip flop

JK flip flop

RS flip flop

none of these

Discussion

MCQ

A CPU generally handles an interrupt by executing an interrupt service routine

as soon as an interrupt is raised

by checking the interrupt register at the end of fetch cycle.

by checking the interrupt register after finishing the execution of the current instruction.

by checking the interrupt register at fixed time intervals.

Discussion

MCQ

Set on less than has the ALU control lines

1100

1010

1101

111

Discussion

MCQ

The registers, ALU and the interconnection between them are collectively called as _____ .

Process route

Information trail

Information path

Data path

Discussion

Banking

Engineering

General

Medical

Question Discussion & Solution

Report Error

Community Discussion

Similar Questions

Report Error

Report Error

Report Error

Report Error

Report Error

More Computer Organization and Architecture Topics

Instruction set architecture

Cache Memory and Pipelining

Machine instructions and Addressing modes

Secondary Memory,Input Output interfce(DMA,Interrupts)

ALU data path and Control Unit

Cache Memory and its design

CPU design

Interrupts

Subroutines and Nesting

Direct Memory Access

PCI BUS

Mixed

Banking

Engineering

General

Medical

Question Discussion & Solution

report Report Error

forum Community Discussion

auto_awesome Similar Questions

report Report Error

report Report Error

report Report Error

report Report Error

report Report Error

category More Computer Organization and Architecture Topics

Instruction set architecture

Cache Memory and Pipelining

Machine instructions and Addressing modes

Secondary Memory,Input Output interfce(DMA,Interrupts)

ALU data path and Control Unit

Cache Memory and its design

CPU design

Interrupts

Subroutines and Nesting

Direct Memory Access

PCI BUS

Mixed

Report Error

Community Discussion

Similar Questions

Report Error

Report Error

Report Error

Report Error

Report Error

More Computer Organization and Architecture Topics