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MCQ

Q.

Which of the following is not a write policy to avoid Cache Coherence?

A

Write through

B

Write within

C

Write back

D

Buffered write

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MCQ

1.

The fetch and execution cycles are interleaved with the help of ________

A

Modification in processor architecture

B

Clock

C

Special unit

D

Control unit

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2.

When the data at a location in cache is different from the data located in the main memory, the cache is called _____________

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Unique

B

Inconsistent

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Variable

D

Fault

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3.

The transfer between CPU and Cache is ______________

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Block transfer

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Word transfer

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Set transfer

D

Associative transfer

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______ have been developed specifically for pipelined systems.

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Utility software

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peed up utilities

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Optimizing compilers

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5.

Which of the following is an efficient method of cache updating?

A

Snoopy writes

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Write through

C

Write within

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Buffered write

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